1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149

/* Copyright (c) [2023] [Syswonder Community]
 *   [Rukos] is licensed under Mulan PSL v2.
 *   You can use this software according to the terms and conditions of the Mulan PSL v2.
 *   You may obtain a copy of Mulan PSL v2 at:
 *               http://license.coscl.org.cn/MulanPSL2
 *   THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 *   See the Mulan PSL v2 for more details.
 */

/// If adding `random-hw` to features, rand()/random() will try to use CPU instruction to generate the random.
/// If CPU doesn't support instructions for random Generation, rand()/random() will return persudo random using LCG algorithm instead;
/// Without feature `random-hw`, rand()/random() will simply return 64-bit persudo random generated from LCG algorithm by default.
/// For x86_64, intel's CPU support `rdrand` instruction since IvyBridge, AMD's CPU support `rdrand` since Ryzen.
/// For aarch64, resigter `rndr` is supported for part of CPU core since ARMv8.5. For more information, you can read: https://developer.arm.com/documentation/ddi0601/2023-06/AArch64-Registers/RNDR--Random-Number?lang=en
/// We can determine whether the CPU supports this instruction by CPUID(x86_64) or ID_AA64ISAR0_EL1(aarch), which is implement in function `has_rdrand()`.
/// As of now, riscv64 does not support generating random numbers through instructions.           
use core::ffi::{c_int, c_long, c_uint};

use core::sync::atomic::{AtomicU64, Ordering::SeqCst};

static SEED: AtomicU64 = AtomicU64::new(0xae_f3);

/// Returns a 32-bit unsigned pseudo random interger using LCG.
fn rand_lcg32() -> u32 {
    let new_seed = SEED
        .load(SeqCst)
        .wrapping_mul(6364136223846793005)
        .wrapping_add(1);
    SEED.store(new_seed, SeqCst);
    (new_seed >> 33) as u32
}

/// Returns a 64-bit unsigned pseudo random interger using LCG.
fn random_lcg64() -> u64 {
    let new_seed = SEED
        .load(SeqCst)
        .wrapping_mul(6364136223846793005)
        .wrapping_add(1);
    SEED.store(new_seed, SeqCst);
    new_seed >> 1
}

/// Sets the seed for the random number generator implemented by LCG.
fn srand_lcg(seed: u64) {
    SEED.store(seed - 1, SeqCst);
}

/// Checking if the CPU core is compatible with hardware random number instructions.
#[cfg(feature = "random-hw")]
fn has_rdrand() -> bool {
    #[cfg(target_arch = "x86_64")]
    {
        let mut ecx: u32;
        unsafe {
            core::arch::asm!(
                "mov eax, 1",
                "cpuid",
                out("ecx") ecx
            )
        }
        ecx & (1 << 30) != 0
    }
    #[cfg(target_arch = "aarch64")]
    {
        let mut id_aa64_isar0_el1: u64;
        unsafe {
            core::arch::asm!(
                "mrs {},ID_AA64ISAR0_EL1",
                out(reg) id_aa64_isar0_el1
            )
        }
        id_aa64_isar0_el1 & (0b1111 << 60) == 0b0001 << 60
    }
    #[cfg(target_arch = "riscv64")]
    {
        false
    }
}

/// Return 64-bit unsigned random interger using cpu instruction
#[cfg(feature = "random-hw")]
fn random_hw() -> u64 {
    let mut _random: u64;

    #[cfg(target_arch = "x86_64")]
    {
        unsafe {
            core::arch::asm! {
                "rdrand {0:r}",
                out(reg) _random
            }
        }
        _random
    }

    #[cfg(target_arch = "aarch64")]
    {
        unsafe {
            core::arch::asm! {
                "mrs {}, s3_3_c2_c4_0", // s3_3_c2_c4_0 is register `rndr`
                out(reg) _random
            }
        }
        _random
    }

    #[cfg(target_arch = "riscv64")]
    {
        panic!("riscv64 has no rdrand instructions")
    }
}

/// Sets the seed for the 32-bit random number generator based on LCG.
#[no_mangle]
pub unsafe extern "C" fn srand(_seed: c_uint) {
    srand_lcg(_seed as u64);
}

/// Returns a 32-bit unsigned random integer
#[no_mangle]
pub unsafe extern "C" fn rand() -> c_int {
    #[cfg(feature = "random-hw")]
    {
        match has_rdrand() {
            true => (random_hw() >> 33) as c_int,
            false => rand_lcg32() as c_int,
        }
    }
    #[cfg(not(feature = "random-hw"))]
    {
        rand_lcg32() as c_int
    }
}

/// Returns a 64-bit unsigned random integer
#[no_mangle]
pub unsafe extern "C" fn random() -> c_long {
    #[cfg(feature = "random-hw")]
    {
        match has_rdrand() {
            true => (random_hw() >> 1) as c_long,
            false => random_lcg64() as c_long,
        }
    }
    #[cfg(not(feature = "random-hw"))]
    {
        random_lcg64() as c_long
    }
}